| Part number: | XCV812E-7BG560I |
| Description: | XCV812E-7BG560I datasheet pdf and Evaluation Boards - Embedded - Complex Logic (FPGA, CPLD) product details from Xilinx stock available at Utmel |
| Manufacturer | Xilinx |
| Encapsulation | - |
| Quantity | 0 |
| RoHS | YES |
| TYPE | DESCRIPTION |
| Surface Mount | YES |
| Number of Terminals | 560 |
| Package Shape | SQUARE |
| JESD-609 Code | e0 |
| Pbfree Code | No |
| ECCN Code | 3A991.D |
| Terminal Finish | Tin/Lead (Sn63Pb37) |
| HTS Code | 8542.39.00.01 |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 225 |
| Terminal Pitch | 1.27 mm |
| Reach Compliance Code | not_compliant |
| Pin Count | 560 |
| JESD-30 Code | S-PBGA-B560 |
| Number of Outputs | 404 |
| Qualification Status | Not Qualified |
| Power Supplies | 1.2/3.6,1.8 V |
| Temperature Grade | INDUSTRIAL |
| Number of Inputs | 404 |
| Organization | 4704 CLBS, 254016 GATES |
| Seated Height-Max | 1.7 mm |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Combinatorial Delay of a CLB-Max | 0.42 ns |
| Number of CLBs | 4704 |
| Number of Logic Cells | 21168 |
| Number of Equivalent Gates | 254016 |
| Length | 42.5 mm |
| Width | 42.5 mm |
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